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- Nanologic combines several emerging technologies to create a breakthrough strategy for computation and computer design:
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Ø Topologic |
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Ø Setlogic |
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Ø Nanoelectronics |
- In addition, nanologic embraces the following technologies, which are consistent (actually they are demanded) with the previous list:
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Ø Analog data |
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Ø Analog arrays |
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Ø Application-specific architecture |
- We describe each of these technologies briefly:
- Topologic means that the topology of the computational circuit is the same as the system being simulated. A fundamental principle of simulation holds that that the closer the model system is in structure and function to the system being simulated, the more efficient (=faster, efficient, etc.) the simulation will be. For instance, a cup of tea is a very efficient simulator of a cup of coffee, but a box full of marbles is poorer, and a digital computer is wildly inefficient (but perhaps convenient, fascinating to modelers, and the only way to sensibly vary parameters).
- Setlogic means that data is represented and manipulated in chunks ("sets"), rather than individual values. At the simplest level, the width of the databus in a digital machine (8-bit...128-bit...) The recent trend toward massively parallel digital computers, while enabling supercomputers with sometimes spectacular performance, does implement setlogic, but only for finite (and rather small) sets. In order to attack hard, but qualitative, problems of human interest, we need circuits that can represent and manipulate infinite sets (continuous functions), hence the need to differentiate setlogic from massively parallel digital logic.
- Nanoelectronics introduces device transfer functions that are neither finite multistate nor linear. Most effort on nanoelectronics is directed toward fabricating devices with simple characteristic functions. On the contrary, the use of more complex core devices provides exponentially higher logic density. Thus, rather than suppress the complex behavior of nanoscale devices, we seek to exploit it. The nanophysical advantages (higher density, etc.) are largely orthogonal to the logical advantages (complex function generation, etc.), hence the performance advantages due to nano-size and nano-behavior can be combined multiplicatively.
- Analog data enables exploiting the complex transfer functions of nanoelectronic devices. The real advantage of analog is that the real-world is, by-and-large, analog; analog circuits are a far better match to the real-world than digital, and this satisfies the primary requirement of efficiency in simulation, namely that the system and its simulator have similar structure (architecture) and function. Furthermore, analog circuits have intrinsic precision that is comparable to the real world (say 103), and that precision is adaptable in real-time. In this sense, digital computers are abysmally inefficient because their data representation bears no relation to any real-world system.
Analog arrays combine the advantages of analog data processing and massive parallelism. This area has recently become a rapidly-growing technology, stemming mostly from the work of Carver Mead at Caltech. Current work ranges from commercially available 4-block analog functional boards to the million-neuron equivalent boards under development by Boahen and co-workers at Stanford and elsewhere. Nanologic seeks the appropriate compromise between complexity of the analog functions and the number of configurable analog blocks that can be put on a chip.
- Application-specific architectures is a long-used approach for increasing performance at the expense of higher development cost and reduced versatility. We hold that computing in the future will require application-specific machines. It is relatively clear that the world economy will support the development of machines configured and optimized for areas such as molecular dynamics, fluid mechanics, neurophysiology, meteorology, and composite materials.
- Combining estimates from the literature and our own estimates of the advantages that accrue from these factors, we obtain the following table of projected enhancements of logical throughput of a nanologic computer over conventional digital computers.
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